1. Field of the Invention
The invention relates to a method for reading out and storing the state from or in a ferroelectric transistor of a memory cell and to a memory matrix.
2. Description of the Related Prior Art
Such a method and such a memory matrix are disclosed in T. Nakamura et al. A Single-Transistor Ferroelectric Memory Cell, IEEE International Solid-State Circuits Conference, ISSCC95, Session 4, Technology Directions: Displays, Photonics and Ferroelectric Memories, pp. 68-69, 1995.
The memory matrix disclosed in T. Nakamura et al. A Single-Transistor Ferroelectric Memory Cell, IEEE International Solid-State Circuits Conference, ISSCC95, Session 4, Technology Directions: Displays, Photonics and Ferroelectric Memories, pp. 68-69, 1995 is a matrix having a multiplicity of memory cells each having a ferroelectric transistor which are connected to one another in a form of a square matrix. Furthermore, the memory matrix has a read-out/storage control device, which can be used to store a state of a ferroelectric transistor of a memory cell in the memory matrix or can be used to read out the present state of the corresponding ferroelectric transistor of the memory cell.
In accordance with the procedure described in T. Nakamura et al. A Single-Transistor Ferroelectric Memory Cell, IEEE International Solid-State Circuits Conference, ISSCC95, Session 4, Technology Directions: Displays, Photonics and Ferroelectric Memories, pp. 68-69, 1995, if a state in a ferroelectric transistor of a memory cell of the memory matrix is stored, erased or read, a corresponding read-out/storage voltage is applied to the corresponding word lines and bit lines. The application of the required read-out/storage voltage also influences further ferroelectric transistors which lie adjacent in the memory matrix and are connected to the ferroelectric transistor whose state is intended to be stored or read out. In this way, it can happen that, as a result of the read-out or storage of a state of one ferroelectric transistor of the memory matrix, a state of a further ferroelectric transistor of the memory matrix is altered erroneously, that is to say unintentionally.
As is described in T. Nakamura et al. A Single-Transistor Ferroelectric Memory Cell, IEEE International Solid-State Circuits Conference, ISSCC95, Session 4, Technology Directions: Displays, Photonics and Ferroelectric Memories, pp. 68-69, 1995, a read-out/storage voltage of Vpp/Vrr is present at the ferroelectric transistor from or in which a state is intended to be read out or stored. In this case, an interference voltage of approximately ±Vpp/2 or ±Vpp/3 is present at the adjacent further ferroelectric transistors connected to the said ferroelectric transistor, and the state of the corresponding further ferroelectric transistor can be erroneously altered by the said interference voltage.
This problem area will be explained below with reference to FIG. 2.
FIG. 2 illustrates a diagram 200 with a profile of the ferroelectric polarization 201 in the gate of a ferroelectric transistor as a function of an applied gate voltage VGS 202. In the diagram 200 the gate voltage 202 is specified in volts ([V]) and the ferroelectric polarization 201 is specified in coulomb/m2 ([C/m2]).
The profile of the ferroelectric polarization 201 as a function of the gate voltage VGS 202 is described by a hysteresis loop 203. As can be gathered from FIG. 2, a customary ferroelectric transistor has two stable polarization states, a first stable polarization state 204 and a second stable polarization state 205. As a result of a change in the applied gate voltage VGS, in particular as a result of an above-described “interference voltage” of Vpp/2 or Vpp/3, the state of the ferroelectric transistor can undergo transition along the hysteresis loop 203 into electrically non-distinguishable polarization states, namely into a first non-distinguishable polarization state 206 and into a second non-distinguishable polarization state 207.
Whereas it is possible in a simple manner to electrically distinguish the first distinguishable polarization state 204 from the second distinguishable polarization state 205, whereby two different states can be realized and identified by the ferroelectric transistor within the memory matrix, such electrical distinguishability is not ensured in the case of the non-distinguishable polarization states 206, 207.
Consequently, as a result of such an interference voltage, the state stored in adjacent further ferroelectric transistors in the memory matrix can be altered or at least become undefined, in other words a polarization state is formed in the corresponding adjacent ferroelectric transistor which cannot reliably be read out, that is to say electrically distinguished.